This question comes from Blindsmyth and others.
In general, anything that is possible via IO pins on the original hardware is possible on the new hardware. The processors are pin compatible. The pin assignment is exactly the same by default for all legacy features. The GPIO test points that existed on the original Core hardware have the same names and assignments. The processor itself has 176 pins. The design attempts to make every potentially useful processor feature available at a test point. There’s a diagram that shows the test point pinout at the bottom of the reference manual page.
The ultimate source of truth about “What can processor pin X do?” is the processor datasheet (linked at the bottom of the reference section). The H7 has several additional peripherals beyond what the F4 offers. The pin assignment established in the original hardware is just one possible variation.